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dsPIC30F
5.4
DSP Engine
5.4.3
SATURATION AND OVERFLOW
The DSP engine consists of a high-speed, single-cycle,
17-bit x 17-bit multiplier, a barrel shifter and a 40-bit
adder/subtractor with two target accumulators, round
and saturation logic, all of which enable efficient
execution of computationally intensive DSP algorithms.
The 17-bit x 17-bit multiplier is also utilized for MCU-
based multiply instructions.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG . This feature greatly simplifies basic
arithmetic operations on 32-bit or 40-bit data.
A block diagram of the DSP engine is shown in
Figure 5-4.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow Status bits
described above, and the user-configured control bits
to determine when to saturate and to what value to
saturate (a 40-bit or a 32-bit value).
In addition to adder/subtractor saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator.
The rounding logic performs a conventional (biased) or
convergent (unbiased) data rounding function during
an accumulator write (store). The Round mode is user-
selectable. Rounding generates a 16-bit, 1.15 data
value, which is passed to the data space write
saturation logic. Data space write saturation ensures
5.4.1
17X17-BIT MULTIPLIER
that the data in the accumulator is written back
The 17 x 17-bit multiplier is capable of signed or
unsigned operation. It can suitably scale its output to
support either 1.31 fractional (Q31) or 32-bit integer
results, thereby diminishing the need to manually
post-process multiplication results for fractional data.
accurately even when rounding is performed. If
rounding is not indicated by the instruction, a truncated
1.15 data value is stored and the least significant word
(lsb) is simply discarded.
5.4.2
40-BIT ACCUMULATORS
The data accumulators have a 40-bit adder/subtractor
with automatic sign-extension logic. It can select one of
two accumulators (A or B) as its pre-accumulation
source and post-accumulation destination. For the ADD
and LAC instructions, the data to be accumulated or
loaded can be optionally scaled via the barrel shifter
prior to accumulation.
The adder/subtractor generates overflow Status bits
SA/SB and OA/OB, which are latched and reflected in
the STATUS Register and can also optionally generate
an Arithmetic Error Trap:
? Overflow from bit 39. This is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
? Overflow into guard bits 32 through 39. This is a
recoverable overflow. This bit (OA/OB) is set
whenever all the guard bits are not identical to
each other.
DS70043F-page 14
? 2005 Microchip Technology Inc.
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